| NOV 21 | 12:00 | Registration Desk Open | |||
| 13:30 |
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| 14:50 | Break | ||||
| 15:10 |
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| 16:30 | Break | ||||
| 17:30 | Welcome Reception (Caf'e Laurel) |
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| NOV 22 | 08:00 | Registration Desk Open | |||
| 08:40 | Plenary Session | ||||
| 09:00 | Keynote 1 How the Test Community can Rise to the Challenge of Chiplets Jeff Rearick / Senior Fellow, AMD (Laurel Ballroom) |
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| 09:50 | Break | ||||
| 10:00 | Keynote 2 Learning by Failing: Test-Thinking for Impactful Machine Learning Trista Chen / Director, Microsoft (Laurel Ballroom) |
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| 10:50 | Break | ||||
| 11:10 | Keynote 3 A Paradigm Shift; From Device to System Testing Daniel F. J. Yang / Director, TSMC (Laurel Ballroom) |
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| 12:00 | Lunch Break | ||||
| 13:30 | Industry Session 1 Latest Technologies and Solutions for Hyperscaler Designs (Laurel Ballroom Salon I) |
Regular Session 1 Reliable Designs (Laurel Ballroom Salon II) |
Regular Session 2 Secure Scan Chain (Chung Kang Room and Wen Hsin Room) |
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| 14:30 | Break | ||||
| 14:40 | Industry Session 2 Driving Intelligent System Design with 3D-IC (Laurel Ballroom Salon I) |
Regular Session 3 Measurement and Calibration for Test (Laurel Ballroom Salon II) |
Regular Session 4 Aging and Reliability (Chung Kang Room and Wen Hsin Room) |
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| 15:40 | Break | ||||
| 16:00 | Industry Session 3 The Test Solutions Addressing the Scalings for Technology, Design and System (Laurel Ballroom Salon I) |
Regular Session 5 Diagnostic and On-line Tests (Laurel Ballroom Salon II) |
Regular Session 6 System Security and Trust (Chung Kang Room and Wen Hsin Room) |
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| 17:00 | Break | ||||
| 18:00 | Banquet (Laurel Ballroom) |
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| NOV 23 | 08:00 | Registration Desk Open | |||
| 08:30 | Industry Session 4 From Chip D&T to Energy-Efficiency (Laurel Ballroom Salon I) |
Regular Session 7 Advanced Test Generation Methods (Laurel Ballroom Salon II) |
Regular Session 8 Machine Learning and Test AI (Chung Kang Room and Wen Hsin Room) |
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| 09:30 | Break | ||||
| 09:40 | Special Session Radiation Effects, Test, and Fault Tolerance (Laurel Ballroom Salon I) |
High School Posters (Laurel Ballroom Salon II) |
Regular Session 9 Error Analysis and Tolerance (Chung Kang Room and Wen Hsin Room) |
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| 10:40 | Break | ||||
| 11:00 | Ph.D. Thesis Competition (Laurel Ballroom Salon I) |
High School Posters (Laurel Ballroom Salon II) |
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| 12:00 | Lunch Break (Laurel Ballroom) |
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| 13:00 | Social Event (13:00 - 17:50) | ||||
Time: 11/21 13:30-14:50pm
Topic: Si-Based Qubits and Cryo-CMOS Control Circuits
Speaker: Jiun-Yun Li / Professor, National Taiwan University
Location: Laurel Ballroom Salon I
Abstract:
Si-based spin qubits are a promising platform for high-fidelity quantum computers for their scalability and VLSI compatibility due to the long spin decoherence. To achieve large-scale quantum computers, cryo-CMOS circuits is required to avoid issues by the electronic controllers at room temperature. Si-based qubits > 1 K enables a quantum system-on-chip (QSOC) including qubit processors and cryo-CMOS controllers. In this tutorial, fundamentals of Si-based qubits will be introduced first, such as material growth, device physics, and spin control / readout. Then the current progress and perspectives of Si-based qubits will be given, followed by the introduction of cryo-CMOS devices and circuits to access to qubits.
Outline
● Introduction of Si-based qubits
● Materials and physics of Si quantum dots
● Characterization of Cryo-CMOS and circuits
Time: 11/21 15:10-16:30pm
Topic: Test and Diagnosis of Quantum Circuits
Speaker: James C. M. Li / Professor, National Taiwan University
Location: Laurel Ballroom Salon I
Abstract:
Quantum circuits (QC) are becoming an important computational technology in many useful applications, such as machine learning, optimization, and cryptography. Testing QC, however, is completely different from testing classical circuits. In this tutorial, we will introduce basic concepts about QC from test engineers' perspective. Then, we will introduce error, noise, and fault models for quantum circuits. Finally, we will propose new test generation and diagnose techniques for quantum circuits.
Outline
● Basic Concepts about Quantum Circuits
● Errors, Noise, and Faults
● Test and Diagnosis of Quantum Circuits
Time: 11/21 13:30-16:30pm
Topic: Addressing Test, Safety, & Security for Connected Automotive ICs
Speakers: Lee Harrison / Siemens EDA
Speakers: Wu Yang / Siemens EDA
Location: Laurel Ballroom Salon II
Abstract:
The exponential growth of electronics in automobiles have stimulated significant innovation towards the development of advanced safety mechanisms. At the same time, automotive ICs are being manufactured in smaller technology nodes, which means maintaining high quality and reliability continues to challenge the safety targets.
As we rise to these new challenges for test, safety and security it has inevitably resulted in advances in the technology we deploy to detect and monitor defects as well as anomalies in both the silicon and the system. Coupled with the requirement to continue this monitoring for the life cycle time of the device rather than at just the manufacturing stage.
This tutorial aims to address the challenges of developing an automotive IC and walk through in detail how advanced test technologies can be used to address these challenges, before looking at the requirements of In-life monitoring and the impact this has on security . Highlighting some of the technologies that can be used to extract data from these automotive devices, safely and securely.
Outline
Part 1 - Introduction
Part 2 - High quality manufacturing test
Part 3 - Functional safety
Part 4 - SLM and In-Life Monitoring
Part 5 - Summary
Time: 11/22 9:00-9:50am
Topic: How the Test Community can Rise to the Challenge of Chiplets
Speaker: Jeff Rearick / Senior Fellow, AMD
Location: Laurel Ballroom
Chair: Jing-Jia Liou / National Tsing Hua University
Abstract:
Heterogeneous integration of multiple chiplets into a single package is emerging as the next step in the progression of Moore's Law. Though this technique shows great promise as a platform for many products, it is accompanied by many new challenges, including several for the test community. This presentation will review the motivation for chiplet-based architectures and show a few examples, discuss some specific challenges associated with testing chiplets and chiplet-based systems, and suggest some activities that the test community must complete to address these issues. The critical role of standardization to create a chiplet ecosystem will be emphasized.
Bio:
Jeff Rearick is a Senior Fellow with Advanced Micro Devices, where he has worked for 16 years leading the DFT Strategy team. Prior to joining AMD, Jeff worked at HP/Agilent for 22 years on DFT methodology and implementation for a variety of microprocessor and networking chips. He served as Editor for the IEEE 1687 standard, currently holds that same role again for the refresh activity for 1687 and well as for both the IEEE P1687.1 and P1687.2 Working Groups, and is a member of the P2427 Working Group. He was a founder of all four of those efforts. He was also a member of the IEEE 1149.6 working group and co-authored the first publication of an implementation of that standard. He has published dozens of other technical papers and presentations, holds over 40 patents, and is an active member of the Test Technology Standards Committee as well as the program committees of the International Test Conference and the European Test Symposium. He earned B.S.E.E and M.S.E.E degrees from Purdue University and the University of Illinois, respectively, and was the recipient of the Bob Madge Innovation Award in 2016 and the Hans Karlsson Award from the IEEE Computer Society in 2018.
Time: 11/22 10:00-10:50am
Topic: Learning by Failing: Test-Thinking for Impactful Machine Learning
Speaker: Trista Chen / Director, Microsoft
Location: Laurel Ballroom
Chair: Harry Chen / Mediatek Inc.
Abstract:
Machine learning has gained tremendous popularity in recent years due to its capabilities in solving complex problems in almost every walk of life, from facial recognition, financial fraud detection to autonomous driving. However, due to its complexity and "black box" nature, deploying a machine learning system to the real-world setting can be challenging. Albert Einstein has once said "anyone who has never made a mistake has never tried anything new". The usefulness of failing, or failing then learning, has been made popular by a software development methodology called Test Driven Development (TDD). TDD converts software requirements to test cases before software is fully developed. It frames how the software intends to work and can reduce the software bugs for up to 90%. Therefore, in this talk, we invite the audience to join the new test-thinking paradigm. With such a new test-thinking, we wish to not only successfully deploy machine learning systems in the real-world but unleash the true potential of machine learning approaches.
Bio:
Trista is a tech executive and an AI scientist. She is currently Director, AI Research Center at Microsoft in Taipei, with research interests in computer vision (CV), human-centered AI, mixed reality, and health AI. In addition to actively publishing 30+ papers and 110+ patents (issued and pending), she won the world championship in USAID Intelligent Forecasting Competition. Previously, Trista held leadership positions at multinational corporations such as Inventec, Intel, and Nvidia and led two startups from incubation to acquisition. As the Chief AI Officer at Inventec, she led the team to obtain the first batch of ISO-13485 medical quality management certificate in Taiwan with a novel AI Software as a Medical Device (SaMD). In addition, she led a successful real-world smart-manufacturing effort in deploying AI supply chain management, quality assurance, and industry 4.0 solutions to day-to-day production lines with annual revenue of 16B USD. At Intel, Trista facilitated the development the world's most widely adopted CV software, OpenCV, which was downloaded 18 million times as of 2021. At Nvidia, she architected Nvidia's first video processor. Trista received her Ph.D. from Carnegie Mellon University and M.S. and B.S. from National Tsing-Hua University.
Time: 11/22 11:10-12:00am
Topic: A Paradigm Shift; From Device to System Testing
Speaker: Daniel F. J. Yang / Director, TSMC
Location: Laurel Ballroom
Chair: Jin-Fu Li / National Central University
Abstract:
Heterogeneous integration, or by its simpler name of "3DIC" is adopting on advanced silicon manufacturing by innovative packaging with wafer level process technology to gain its power, performance and area benefit. However the 3DIC architecture will continue to drive the Testing complexity. From the testing categories of testing flow, test content, defect learning, test handling and test application all are new challenges that need innovative approaches for testing fundamental functions; to screen defect, to characterize the performance, to detect failure process. There are many focuses, like KGD/KGS/KGP and SLT test strategy to achieve the lower test cost by optimizing the stacking process. What the industry standard for die level test access, also what the test content to support the trade-off between test patterns, test bandwidth and test quality. The defect learning for advanced silicon and packaging to fast bring up through faster PFA, defect isolation and yield improvement. The test contact while the growing bump count and high speed to achieve an optimized Power Integrity and Signal Integrity for interface design. Even the thermal management and mechanical integrity make the Testing become more difficult. 3DIC testing has to enable the heterogeneous integration with appropriate solutions by new collaboration models across industry parties to ensure its success.
Bio:
Daniel Yang is currently as head of testing technology and service division of TSMC. He established many new operation sites and held various technical and managerial positions in the field of testing over 35 years. As foundry testing, Daniel Yang conducted many technical solutions on the integration of probing interface including probe card technology to enable more test coverage on wafer sort stage. Across the different applications of logic and RF to enable silicon and packaging testability through test characterization, data mining solution and optimized process flow to ensure testing coverage while AI and Automotive testing requiring wafer level known good die and heterogeneous testing solutions.
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